AlCu and its related alloys are preferred alloys for forming interconnections on electronic devices such as integrated circuit chips. The amount of Cu in AlCu is typically in the range from 0.3 to 4 percent.
Replacement of AlCu by Cu and Cu alloys as chip interconnection material results in advantages of performance. Performance is improved because the resistivity of Cu and certain copper alloys is less than the resistivity of AlCu; thus narrower lines can be used and higher wiring densities will be realized.
The advantages of Cu metallization have been recognized by the semiconductor industry. In fact, the semiconductor industry is rapidly moving away from aluminum and is adopting copper as the material of choice for chip interconnects because of its high conductivity and improved reliability.
Manufacturing of chip interconnects involves many process steps that are interrelated. In particular, copper interconnects are manufactured using electroplating in a process called “Dual Damascene” in which a via and a line are fabricated together in a single step. The electroplating process, typically, employs a plating solution composed of cupric sulfate salt, sulfuric acid, inorganic and organic additives that control the process such that the rate of copper electrodeposition is differentially inhibited along the sidewall of a small feature, resulting in preferential deposition at the bottom wall of the feature.
This phenomenon is called superfilling.
A few of the important integration challenges that need to be overcome to successfully fabricate Dual Damascene copper interconnects are assuring the continuity of the barrier and seed layer films and providing a copper electroplating process capable of producing seamless and void-free deposits at the feature sidewalls and bottom wall of the feature and along the center of the wiring. Furthermore, the International Technology Roadmap for Semiconductors, 1999 Edition, calls for smaller via diameters and higher aspect ratios in future interconnect metallizations.
With the shrinking dimensions there is a continuing challenge to fill these features with copper without a seam or void. In Dual Damascene fabrication of features with linewidths of 0.25 μm or smaller, typically a via and a line have to be filled in one process step employing copper electroplating. The applied current is carried through a thin seed copper layer. Often, the seed layer is extremely thin, possibly discontinuous and oxidized and thus it is not capable of carrying the electroplating current reliably within small features of high aspect ratios. In sub-micron vias, which are typically more difficult to fill than lines, the rate of diffusion of the cupric ions dissolved in the plating solution is too low to keep up with the rate of reduction of cupric ions at the metal surface. As a result, the cupric ion concentration within a via becomes much lower than the cupric ion bulk concentration and the concentration overpotential becomes large. The superfilling capability of the plating solution provided by the organic additives cannot overcome the large concentration overpotential caused by the depletion of the cupric ion. These phenomena manifest themselves as voids along the sidewall of the features, two types of defects, caused by missing copper seed layer, and voids or seams along the feature centerline, caused by the depletion of the cupric ion within the via.
Accordingly, there exists a need to provide a copper electroplating process that can accomplish Dual Damascene plating at small features without internal seams or voids.